Host-side radio endpoint for a deliberately configured remote-I/O protocol; it is not a transparent wire replacement.
Baseline documentation snapshot: 2026-10-11, before the requested connector/protection/usability revision program. New revision features require their own reviewed source and qualification evidence.
This page documents an unqualified engineering study, not a released or tested product. Saved CAD, renders and automated checks do not establish a safe assembly, compatible cable, firmware support or a usable current rating.
Board-specific qualification limits: Retained ERC/DRC/opens/parity and assembly-shape checks zero;88 checklist items unsigned. Firmware OE/link-loss, partial-power, RF, host budget, debug, exact stock and physical qualification open.
The canonical repository connector contract is pin 1 = +3.3 V, pin 2 = +5 V, pin 10 = GND. Current Smoothie V2 Prime web material appears to describe a conflicting header assignment; the physical target header must be continuity-checked against its authoritative schematic before KiCad release. The table below expresses design intent against the repository’s canonical contract, not proof of the live board pinout.
| Pin | Canonical role | Assigned function |
|---|---|---|
| 1 | +3.3V | +3.3 V rail |
| 2 | +5V | +5 V rail |
| 3 | GPIO! / type-specific | Mode GPIO0 / provisioning GPIO |
| 4 | type-specific | Mode TX or GPIO1 |
| 5 | type-specific | Mode RX or GPIO2 |
| 6 | type-specific | Mode GPIO3 / CTS / CS |
| 7 | type-specific | Mode GPIO4 / RTS / MOSI / PWM |
| 8 | type-specific | Mode GPIO5 / SDA / MISO |
| 9 | type-specific | Mode GPIO6 / SCL / SCK |
| 10 | GND | Ground |
Power off before connecting or changing jumpers. Verify pin 1, signal direction, supply voltage and ground at both ends of every cable. A mechanically fitting connector is not proof of electrical compatibility. If a host pin mapping or current allocation remains unresolved in the design record, do not connect the board until it is resolved.
The following are specification requirements or study assumptions; they are not measured operating ratings. A newer selected-revision note takes precedence over historical draft options.
The design describes the following protection intent. Check the selected schematic and remaining qualification gates before relying on it:
See current review. Retain v10 ATSAMD21E18A/nRF24L01+ interoperability and already adopted SN74CB3Q3245 bus isolation. Integrated nRF52832 requires unsupplied protocol/firmware migration. Existing V1-compatible bypass consolidation retained; no IC-stock successor. Current selected v10; retained native/stock/physical qualification limits remain explicit.
Use the configuration and firmware contract for the exact selected revision. Do not copy another module’s socket assignments or assume that an unused pin is available. First-article work must verify source selection, reset/unplug behavior, cable orientation and the actual load or sensor interface before normal operation.
The following are requirements for the next design iterations; this page does not claim they are already fitted:
Documentation route: smoothieware.org/extensions/wireless-series-master.
The 2026-10-11 upgrade program has saved additional candidates v11, v12, v13. These studies preserve the historical design described above. Their connector, LED, mechanical and protection changes are revision-specific and remain unqualified.
See the per-board changes, failures and remaining work and mandatory family specification. Use the source hash and native check for the exact candidate being reviewed; do not infer hardware ratings from a rendered population.
The three additional revisions are v11, v12, v13. They are engineering studies; saved CAD and renders do not release the hardware. The latest candidate is described below. Older baseline notes above remain historical.
7e78f17eff86bef945feb82d979ce93fcdc8adc4aa58c7669be089c9d32f6438.PinHeader_1x04_P2.54mm_Vertical. Fit only the selected population; check its pin map and voltage in the design record.Applicable protection, current-path, thermal, pinout, cable access and physical tests remain open wherever the linked board record has not verified them. A zero native-error count does not close those gates.
Protected source v13; current PCB SHA-256 3ebeab631adafcb91e2c705f9972ce772818bd22bb09b81b3740ca62f0af920c. Fresh native checks: zero enabled errors, opens, schematic mismatches and ERC findings; 3 PCB warnings remain. Electrical geometry/project rules unchanged; 68 historical files, 66 model entries,17 exports and12 current population images verified. All12 populated/bare views inspected. Full documentation URL is readable in the current renders. Physical qualification remains open; no price or area savings claimed.