Integrate a USB-device-to-3.3 V UART bridge between a USB-B connector and a U socket.
Baseline documentation snapshot: 2026-10-11, before the requested connector/protection/usability revision program. New revision features require their own reviewed source and qualification evidence.
This page documents an unqualified engineering study, not a released or tested product. Saved CAD, renders and automated checks do not establish a safe assembly, compatible cable, firmware support or a usable current rating.
Board-specific qualification limits: Retained native ERC/strict DRC/opens/parity and ordinary drill/mask checks zero; 130 checklist and all270 rule items unsigned. USB impedance/eye, enumeration, 3 Mbaud, backfeed, EMI and physical qualification open.
The selected v11 contract uses the repository-canonical connector rule: pin 1 is +3.3 V, pin 2 is +5 V, and pin 10 is GND. Actual host marking, mating face, cable continuity, and the full signal map must be checked against the target hardware before connection; this document does not resolve conflicting secondary documentation.
| Pin | Function | Design note |
|---|---|---|
| 1 | +3.3 V | Canonical fixed rail. |
| 2 | +5 V | Canonical fixed rail. |
| 3 | GPIO! | Board mapping; validate against current V2 hardware before layout. |
| 4 | TX | Board mapping; validate against current V2 hardware before layout. |
| 5 | RX | Board mapping; validate against current V2 hardware before layout. |
| 6 | GPIO/pass-through | Board mapping; validate against current V2 hardware before layout. |
| 7 | UN | Board mapping; validate against current V2 hardware before layout. |
| 8 | UN | Board mapping; validate against current V2 hardware before layout. |
| 9 | UN | Board mapping; validate against current V2 hardware before layout. |
| 10 | GND | Canonical fixed rail. |
Power off before connecting or changing jumpers. Verify pin 1, signal direction, supply voltage and ground at both ends of every cable. A mechanically fitting connector is not proof of electrical compatibility. If a host pin mapping or current allocation remains unresolved in the design record, do not connect the board until it is resolved.
The following are specification requirements or study assumptions; they are not measured operating ratings. A newer selected-revision note takes precedence over historical draft options.
The design describes the following protection intent. Check the selected schematic and remaining qualification gates before relying on it:
The selected study includes USB ESD and domain-isolation components. Verify ESD return path, VBUS current limiting, decoupling placement, translator sequencing, UART series behavior, and all one-side-unpowered states on the assembled design.
See current review. Retain v11 FT231XS and already adopted TXU0202DCUR two-direction translator; no demonstrated CP2102N/CH340C benefit. Conditional V1 bypass/bias reuse, preserving actual R4 100 kΩ. No IC-stock successor. Current selected v11; retained native/stock/physical qualification limits remain explicit.
Use the configuration and firmware contract for the exact selected revision. Do not copy another module’s socket assignments or assume that an unused pin is available. First-article work must verify source selection, reset/unplug behavior, cable orientation and the actual load or sensor interface before normal operation.
The following are requirements for the next design iterations; this page does not claim they are already fitted:
Documentation route: smoothieware.org/extensions/usb-serial-breakout.
The 2026-10-11 upgrade program has saved additional candidates v12, v13, v14. These studies preserve the historical design described above. Their connector, LED, mechanical and protection changes are revision-specific and remain unqualified.
See the per-board changes, failures and remaining work and mandatory family specification. Use the source hash and native check for the exact candidate being reviewed; do not infer hardware ratings from a rendered population.
The three additional revisions are v12, v13, v14. They are engineering studies; saved CAD and renders do not release the hardware. The latest candidate is described below. Older baseline notes above remain historical.
d890670c83de883aa83f5a900cdcb288f2fa6a110365b91e8856f8ec7913ff2b.Applicable protection, current-path, thermal, pinout, cable access and physical tests remain open wherever the linked board record has not verified them. A zero native-error count does not close those gates.
Protected source v14; current PCB SHA-256 d060d8ec5a6d71a2f95d6aec38067c934b7383c1bbd31d7ec5200b79dff6bec1. Fresh checks: zero enabled errors/opens/parity/ERC findings; 16 PCB warnings. Electrical geometry, project rules and 27 historical files unchanged. Verified 23 model entries, 17 exports and 6 current population views, all inspected. Full documentation URL readable. Exact authored library/models restored; physical model seating remains unqualified Inherited native warnings and enabled-rule exclusions remain explicit Physical/thermal/current/connector-fit qualification open No priced or area savings established by annotation candidate.