Adapt a bounded list of legacy control panels to current V2 through explicitly selected Gadgeteer interfaces.
Baseline documentation snapshot: 2026-10-11, before the requested connector/protection/usability revision program. New revision features require their own reviewed source and qualification evidence.
This page documents an unqualified engineering study, not a released or tested product. Saved CAD, renders and automated checks do not establish a safe assembly, compatible cable, firmware support or a usable current rating.
Board-specific qualification limits: Retained native geometry/ERC/parity pass with 14 opens; panel firmware, host, enclosure, exact stock and physical qualification remain open.
The retained v08 design uses the repository-canonical 10-pin mapping: pin 1 is +3.3 V, pin 2 is +5 V, and pin 10 is GND. The physical host marking, mating face, cable continuity, and full pin map remain unverified; inspect the actual target hardware before connection because documentation sources conflict.
| Pin | Function |
|---|---|
| 1 | +3.3 V canonical; function TBD |
| 2 | +5 V canonical; panel power candidate |
| 3 | TBD display/control |
| 4 | TBD display/control |
| 5 | TBD display/control |
| 6 | TBD display/control |
| 7 | TBD display/control |
| 8 | TBD display/control |
| 9 | TBD display/control |
| 10 | GND |
Power off before connecting or changing jumpers. Verify pin 1, signal direction, supply voltage and ground at both ends of every cable. A mechanically fitting connector is not proof of electrical compatibility. If a host pin mapping or current allocation remains unresolved in the design record, do not connect the board until it is resolved.
The following are specification requirements or study assumptions; they are not measured operating ratings. A newer selected-revision note takes precedence over historical draft options.
The design describes the following protection intent. Check the selected schematic and remaining qualification gates before relying on it:
ESD at panel/user connectors, current-limited panel power, no-backfeed source selection and defined reset states for backlight/enable.
See current review. Retain v10 ATmega328P/74AHCT125/74LVC125 legacy-panel interface; SSD1306 changes the panel/firmware contract. Conditional V1 0603 bypass and bias reuse; no IC-stock successor. Current selected v10; retained native/stock/physical qualification limits remain explicit.
Use the configuration and firmware contract for the exact selected revision. Do not copy another module’s socket assignments or assume that an unused pin is available. First-article work must verify source selection, reset/unplug behavior, cable orientation and the actual load or sensor interface before normal operation.
The following are requirements for the next design iterations; this page does not claim they are already fitted:
Documentation route: smoothieware.org/extensions/universal-panel-adapter.
The 2026-10-11 upgrade program has saved additional candidates v11, v12, v13. These studies preserve the historical design described above. Their connector, LED, mechanical and protection changes are revision-specific and remain unqualified.
See the per-board changes, failures and remaining work and mandatory family specification. Use the source hash and native check for the exact candidate being reviewed; do not infer hardware ratings from a rendered population.
The three additional revisions are v11, v12, v13. They are engineering studies; saved CAD and renders do not release the hardware. The historical v13 candidate is described below; the second-round v18 candidate has its own source-bound results further down.
b6e283c992b7afe39c02f8581699c87da8595dd01e0b6f1d3caf2caa3c47a967.Applicable protection, current-path, thermal, pinout, cable access and physical tests remain open wherever the linked board record has not verified them. A zero native-error count does not close those gates.
The protected v17 circuit is retained in v18 native CAD. This revision corrects titles and version labels, strengthens headings and clears silkscreen from jumper copper and artwork. It adds no components and claims no board-area or purchasing saving.
Independent final-source checks report zero enabled design-rule errors, open connections, schematic-parity findings and electrical-rule findings. Layout warnings fell20→9: seven font-thickness and two library-mismatch warnings remain. Electrical geometry, complete pads/component maps, schematics and electrical rule settings are unchanged; all95 files of v17 were preserved. No ignored categories or explicit exclusions hide failures in these checks.
All six normal-population populated/bare top, bottom and isometric views were hash-verified and inspected. This role currently declares no alternative small-connector population; applicable connector conversion remains a design-review requirement. A schematic SVG and validated PDF, BOM/positions, Gerbers and drill files are exported for engineering review. Gerber metadata still carries inherited revision v10 and must be reconciled before any manufacturing release.
PCB SHA-256: 815eed1b604d9e11b2620d4afae5076bb711718c38422bd8922c33f98c701da6. See the second-round work and remaining requirements. Panel firmware, actual host pin maps, cable budgets, enclosure fit, power/fault behavior, assembly and thermal qualification remain open. This candidate is not fabrication-approved.
The V19 engineering candidate restores the original 100 × 64.6 mm nominal board outline and integrates 39 external-input protection parts into the original envelope (38 on the underside and one diode on the front). All 121 footprints and the complete functional schematic are retained. The keyed host supply already feeds logic directly; it does not need another input-protection stage. The separate loose external input retains its TPS26600 current limit, UV/OV cutoff, slew control, polarity handling and disableable fault indicators. Full-track native checks and schematic parity report zero errors or open connections, and ERC is clear. All six populated/bare views are freshly exported and visually reviewed with no missing models. The layout is unaccepted pending drill-clearance repair and remote verification: five of its twenty warnings are new hole-to-hole violations (zero in V18), including 0.20 mm GND-via separation against a 0.2495 mm minimum and 0.00 mm via-to-J8 plated-hole separation. Zero enabled errors and clear ERC do not waive these physical regressions. The current exports and renders depict this unaccepted candidate. Physical, thermal and external-input behavior remain unqualified. This candidate is not released for fabrication or assembly.