Measure one K-type thermocouple with a cold-junction-compensated SPI converter.
The v15 engineering record describes a new unqualified multi-type thermocouple candidate. The historical MAX31855K read-only K-type revisions remain available. This newer section takes precedence for v15 over the baseline snapshot below.
MAX31856MUD+ supports K/J/N/R/S/T/E/B types, programmable 50/60 Hz filtering and register-based configuration/fault reporting. Its board remains 40 × 30 mm, with the same host connectors and mounting positions, and three additional filter/bypass capacitors. Native ERC, enabled full-track DRC, opens, schematic parity and exact component-contract findings are zero. Six fresh inspected renders, schematic PDF, BOM, placement and candidate manufacturing exports accompany the revision.
For v15, host pin 7 MOSI connects to the converter rather than being pass-through only. A MAX31856 register driver must configure type, filtering and conversions and poll faults; the old MAX31855 read-only transaction is incompatible. No firmware change is supplied. Use 3.0–3.6 V on the converter rail; allow up to 2 mA plus 0.33 mA while CS is selected, and verify total host/chain allocation. The +5 V rail is only passed through. Keep downstream CS jumper JP6 open unless an independently addressed chain arrangement has been verified.
This is not a fabrication release or a measured temperature-accuracy claim. Cold-junction gradients, thermocouple wire/connector choice, input faults, cable/host power-order behavior, ESD/EMC, exact assembly land/stencil approval and physical fit remain unqualified. Applicable schematic/layout checklist and family requirements remain unsigned where explicitly recorded. There is no Gadgeteer I²C mode, so this SPI-only revision does not require Qwiic.
Baseline documentation snapshot: 2026-10-11, before the requested connector/protection/usability revision program. New revision features require their own reviewed source and qualification evidence.
This page documents an unqualified engineering study, not a released or tested product. Saved CAD, renders and automated checks do not establish a safe assembly, compatible cable, firmware support or a usable current rating.
Board-specific qualification limits: Actualv11 retained ERC/strictgeometry/opens/parity/ordinaryassembly0;130checklistunsigned,coldjunction/fault/host/calibration/physical open.
The table below uses the repository-canonical connector rule: pin 1 is +3.3 V, pin 2 is +5 V, and pin 10 is GND. Do not release a schematic from this table until it is reconciled pin-by-pin with the current V2 Prime connector implementation; current web documentation presents a conflicting ordering.
| Pin | Function | Design note |
|---|---|---|
| 1 | +3.3 V | Canonical fixed rail. |
| 2 | +5 V | Canonical fixed rail. |
| 3 | GPIO!/DRDY unused | Board mapping; validate against current V2 hardware before layout. |
| 4 | GPIO unused | Board mapping; validate against current V2 hardware before layout. |
| 5 | GPIO unused | Board mapping; validate against current V2 hardware before layout. |
| 6 | CS | Board mapping; validate against current V2 hardware before layout. |
| 7 | MOSI pass-through | Board mapping; validate against current V2 hardware before layout. |
| 8 | MISO | Board mapping; validate against current V2 hardware before layout. |
| 9 | SCK | Board mapping; validate against current V2 hardware before layout. |
| 10 | GND | Canonical fixed rail. |
Power off before connecting or changing jumpers. Verify pin 1, signal direction, supply voltage and ground at both ends of every cable. A mechanically fitting connector is not proof of electrical compatibility. If a host pin mapping or current allocation remains unresolved in the design record, do not connect the board until it is resolved.
The following are specification requirements or study assumptions; they are not measured operating ratings. A newer selected-revision note takes precedence over historical draft options.
The design describes the following protection intent. Check the selected schematic and remaining qualification gates before relying on it:
Low-capacitance ESD/protection compatible with thermocouple error budget; do not clamp thermocouple inputs with an unvalidated junction.
See current review. Retain MAX31855K; defer MAX31856; decline AD8495; conditional V1 C0603 bypass reuse; no new version Current selected v11; retained native/stock/physical qualification limits remain explicit.
Use the configuration and firmware contract for the exact selected revision. Do not copy another module’s socket assignments or assume that an unused pin is available. First-article work must verify source selection, reset/unplug behavior, cable orientation and the actual load or sensor interface before normal operation.
The following are requirements for the next design iterations; this page does not claim they are already fitted:
Documentation route: smoothieware.org/extensions/spi-thermocouple-breakout.
The 2026-10-11 upgrade program has saved additional candidates v12, v13, v14. These studies preserve the historical design described above. Their connector, LED, mechanical and protection changes are revision-specific and remain unqualified.
See the per-board changes, failures and remaining work and mandatory family specification. Use the source hash and native check for the exact candidate being reviewed; do not infer hardware ratings from a rendered population.
The three additional revisions are v12, v13, v14. They are engineering studies; saved CAD and renders do not release the hardware. The latest candidate is described below. Older baseline notes above remain historical.
ce0ab8cbe898ccb55de15b1dd293f6fe2105410fcde1625bf6b358bf40614997.Applicable protection, current-path, thermal, pinout, cable access and physical tests remain open wherever the linked board record has not verified them. A zero native-error count does not close those gates.
Protected source v15; current PCB SHA-256 6f528cd7fcdabc5548466ec9de23ee2298a2cd4323a806ccf6344bb73753e4ad. Fresh checks: zero enabled PCB errors/opens/parity and ERC errors; 0 PCB warnings. Electrical geometry, project rules and 40 historical files unchanged. Verified 10 model entries, 17 exports and 6 current population views, all inspected. Full documentation URL readable. Board-local shared Samtec dependency hash rechecked unchanged; physical thermocouple/interface qualification open Inherited native warnings and enabled-rule exclusions remain explicit Physical/thermal/current/connector-fit qualification open No priced or area savings established by annotation candidate.