Measure one PT100 RTD using a dedicated SPI RTD converter and permit multiple uniquely selected boards on one SPI bus.
Baseline documentation snapshot: 2026-10-11, before the requested connector/protection/usability revision program. New revision features require their own reviewed source and qualification evidence.
This page documents an unqualified engineering study, not a released or tested product. Saved CAD, renders and automated checks do not establish a safe assembly, compatible cable, firmware support or a usable current rating.
Board-specific qualification limits: v13 retained strictnative/ordinaryassembly0;99checklistunsigned,diagnosticvoltage/RTDlead/calibration/host/thermal/physical open.
The following is the repository-canonical 10-pin mapping for the selected/candidate socket arrangement. Pin 1 is +3.3 V, pin 2 is +5 V, and pin 10 is GND. Current V2 Prime documentation describes a different physical rail placement; do not create footprints, cables, or copper until the real target hardware is inspected and this discrepancy is closed.
| Pin | Function |
|---|---|
| 1 | +3.3 V MAX31865 rail |
| 2 | +5 V unused |
| 3 | Fault/DRDY GPIO candidate |
| 4 | CS-selection GPIO candidate |
| 5 | Additional CS/pass-through GPIO |
| 6 | MAX31865 CS |
| 7 | MOSI/SDI |
| 8 | MISO/SDO |
| 9 | SCK |
| 10 | GND |
Power off before connecting or changing jumpers. Verify pin 1, signal direction, supply voltage and ground at both ends of every cable. A mechanically fitting connector is not proof of electrical compatibility. If a host pin mapping or current allocation remains unresolved in the design record, do not connect the board until it is resolved.
The following are specification requirements or study assumptions; they are not measured operating ratings. A newer selected-revision note takes precedence over historical draft options.
The design describes the following protection intent. Check the selected schematic and remaining qualification gates before relying on it:
Sensor-line series impedance/filter per MAX31865 guidance, ESD at terminal, supply decoupling and optional SPI series damping. Preserve converter fault detection.
See current review. Retain MAX31865AAP+ digitalRTD interface and400Ω0.1%lowTCRreference. ADS1220/ADS124S08 changesexcitation/register/calibrationcontract;no qualified stocked precision/100V0805 match,no successor. Current selected v13; retained native/stock/physical qualification limits remain explicit.
Use the configuration and firmware contract for the exact selected revision. Do not copy another module’s socket assignments or assume that an unused pin is available. First-article work must verify source selection, reset/unplug behavior, cable orientation and the actual load or sensor interface before normal operation.
The following are requirements for the next design iterations; this page does not claim they are already fitted:
Documentation route: smoothieware.org/extensions/spi-pt100-amplifier-board.
The 2026-10-11 upgrade program has saved additional candidates v14, v15, v16. These studies preserve the historical design described above. Their connector, LED, mechanical and protection changes are revision-specific and remain unqualified.
See the per-board changes, failures and remaining work and mandatory family specification. Use the source hash and native check for the exact candidate being reviewed; do not infer hardware ratings from a rendered population.
The three additional revisions are v14, v15, v16. They are engineering studies; saved CAD and renders do not release the hardware. The latest candidate is described below. Older baseline notes above remain historical.
70f175b8caf3d7faa7cb33b7e00189e6421ad5ace9739416fee31aec77d389d7.Applicable protection, current-path, thermal, pinout, cable access and physical tests remain open wherever the linked board record has not verified them. A zero native-error count does not close those gates.
Protected source v16; current PCB SHA-256 cc99ad4931cd1e0a647389a0d34d085c71c27334645d71fc1f2c5489211a30c9. Fresh checks: zero enabled PCB errors/opens/parity and ERC errors; 9 PCB warnings. Electrical geometry, project rules and 47 historical files unchanged. Verified 13 model entries, 19 exports and 6 current population views, all inspected. Full documentation URL readable. Nine inherited lettering warnings remain; PT100 only, not thermocouple Inherited native warnings and enabled-rule exclusions remain explicit Physical/thermal/current/connector-fit qualification open No priced or area savings established by annotation candidate.