Fan one S socket into four independently selected downstream S sockets while preventing unselected devices from loading or driving the shared bus.
Baseline documentation snapshot: 2026-10-11, before the requested connector/protection/usability revision program. New revision features require their own reviewed source and qualification evidence.
This page documents an unqualified engineering study, not a released or tested product. Saved CAD, renders and automated checks do not establish a safe assembly, compatible cable, firmware support or a usable current rating.
Board-specific qualification limits: Current v10 retained source checks/ordinaryassembly clean;original88×52outline target,host/cable timing,poweredoff isolation,exact stock and physical qualification remain open.
The table is the saved J1 input mapping. Reconcile physical host and cable continuity with the authoritative target board before use.
| Pin | Function | Design note |
|---|---|---|
| 1 | +3.3 V | Canonical fixed rail. |
| 2 | +5 V | Canonical fixed rail. |
| 3 | CS1 | Board mapping; validate against current V2 hardware before layout. |
| 4 | CS2 | Board mapping; validate against current V2 hardware before layout. |
| 5 | CS3 | Board mapping; validate against current V2 hardware before layout. |
| 6 | CS4 | Board mapping; validate against current V2 hardware before layout. |
| 7 | MOSI | Board mapping; validate against current V2 hardware before layout. |
| 8 | MISO | Board mapping; validate against current V2 hardware before layout. |
| 9 | SCK | Board mapping; validate against current V2 hardware before layout. |
| 10 | GND | Canonical fixed rail. |
J2–J5 outputs each use pin1 +3.3 V, pin2 +5 V, pins3–5 NC, pin6 that port’s CS, pin7 MOSI, pin8 MISO, pin9 SCK and pin10 GND. CS and rails pass through directly; SCK/MOSI/MISO pass through the selected switch cell. The optional six-pin Adafruit headers are not populated in this candidate.
Power off before connecting or changing jumpers. Verify pin 1, signal direction, supply voltage and ground at both ends of every cable. A mechanically fitting connector is not proof of electrical compatibility. If a host pin mapping or current allocation remains unresolved in the design record, do not connect the board until it is resolved.
The following are specification requirements or study assumptions; they are not measured operating ratings. A newer selected-revision note takes precedence over historical draft options.
The design describes the following protection intent. Check the selected schematic and remaining qualification gates before relying on it:
U5–U9 TPD4E1U06DCKR provide the selected ESD network at the five sockets. Rails are shared pass-through without per-port current limiting. Reset pulls, switch Ioff, clamp injection and independent peripheral supply states require assembled verification. Simultaneous CS assertions are not rejected in hardware.
See current review. Retain four SN74CB3Q3125; V2 TPD4E1U06DCKR applied in retained v07 and V1 33.2 ohm 1% R0603 damping in v08; no new version Current selected v10; retained native/stock/physical qualification limits remain explicit.
Use the configuration and firmware contract for the exact selected revision. Do not copy another module’s socket assignments or assume that an unused pin is available. First-article work must verify source selection, reset/unplug behavior, cable orientation and the actual load or sensor interface before normal operation.
The following are requirements for the next design iterations; this page does not claim they are already fitted:
Documentation route: smoothieware.org/extensions/spi-hub.
The 2026-10-11 upgrade program has saved additional candidates v11, v12, v13. These studies preserve the historical design described above. Their connector, LED, mechanical and protection changes are revision-specific and remain unqualified.
See the per-board changes, failures and remaining work and mandatory family specification. Use the source hash and native check for the exact candidate being reviewed; do not infer hardware ratings from a rendered population.
The three additional revisions are v11, v12, v13. They are engineering studies; saved CAD and renders do not release the hardware. The latest candidate is described below. Older baseline notes above remain historical.
edfd93eb41f9a20164159080042d73b3e183e8c4301d3301ab17415fca54c349.Applicable protection, current-path, thermal, pinout, cable access and physical tests remain open wherever the linked board record has not verified them. A zero native-error count does not close those gates.
Protected source v13; current PCB SHA-256 5749c4801853b7abeb7621203ef34923190d2eb57b6e4dbacc4a5c5ac7738439. Fresh checks: zero enabled PCB errors/opens/parity and ERC errors; 9 PCB warnings. Electrical geometry, project rules and 31 historical files unchanged. Verified 51 model entries, 17 exports and 6 current population views, all inspected. Full documentation URL readable. Inherited dangling track warning remains Inherited native warnings and enabled-rule exclusions remain explicit Physical/thermal/current/connector-fit qualification open No priced or area savings established by annotation candidate.