Seven-channel mechanical-relay output study for specified DC loads. Coil indicators show command/coil state; they do not prove that a contact has switched or that a connected load is drawing current.
Current retained annotation candidate: v23, 2026-10-13. Current uppercase revision labels, a reflowed documentation link and a contact-terminal guide improve readable wiring information without changing circuitry, relay mechanism, copper, isolation slots/lands, protective features or mounting. Contact terminals are 1 = NO, 2 = NC, 3 = C; coil-drive LEDs do not prove contact position.
Fresh full-track native checks report zero enabled errors, opens and schematic-parity errors; design-rule warnings changed from 10 to 8, with no category increase. Seven inherited schematic footprint-link warnings remain. Six normal-population views were inspected, all 149 declared model instances resolve, and 17 source-bound exports were verified. Existing dense edge markings still need cleanup. This is an unqualified engineering candidate: fabrication release, physical assembly, current/thermal/load/isolation, host and cable/enclosure qualification remain withheld.
This page documents an unqualified engineering study, not a released or tested product. Saved CAD, renders and automated checks do not establish a safe assembly, compatible cable, firmware support or a usable current rating.
The retained design record states:
V15 retains seven conditional V1-family5.6k/10%/0603 coil indicators, collinear copper cleanup, side-correct factory/indicator/hardware notes, exact local library associations and a readable grid-aligned schematic. The rejected0.70mm widening trials are restored to original0.60mm trunks; narrower local RPW escapes remain explicit. The 220×100mm envelope and soldered optical architecture are retained. All156 component decisions assess both BOMs and TPL7407L/DRV8860 without forcing a control/isolation redesign. Actual stock lot, rating and quantity remain conditional. Earlier4.7k indicator descriptions below describe the baseline, superseded only for R_IND1–R_IND7.
Board-specific qualification limits: v15 strictERC/geometry/parity0/sixopens;80BOM identityfields blank,coil/host/thermal/fault/stock/physical signoff open.
The exact connector orientation, pin mapping and supply ownership must be taken from the selected revision’s schematic and connection specification. Do not infer wiring from the connector shape.
Power off before connecting or changing jumpers. Verify pin 1, signal direction, supply voltage and ground at both ends of every cable. A mechanically fitting connector is not proof of electrical compatibility. If a host pin mapping or current allocation remains unresolved in the design record, do not connect the board until it is resolved.
See current review. Retain optical/AO3400A/SS16,TPS259474 and isolated VRB coil architecture. Existing seven conditional V1 5.6k10%0603 indicator conversions retained;TPL7407L/DRV8860 benefit not demonstrated,no IC-stock successor. Current selected v15; retained native/stock/physical qualification limits remain explicit.
Use the configuration and firmware contract for the exact selected revision. Do not copy another module’s socket assignments or assume that an unused pin is available. First-article work must verify source selection, reset/unplug behavior, cable orientation and the actual load or sensor interface before normal operation.
The following are requirements for the next design iterations; this page does not claim they are already fitted:
Documentation route: smoothieware.org/extensions/seven-channel-dc-mechanical-relay.
The 2026-10-11 upgrade program has saved additional candidates v16, v17, v18. These studies preserve the historical design described above. Their connector, LED, mechanical and protection changes are revision-specific and remain unqualified.
See the per-board changes, failures and remaining work and mandatory family specification. Use the source hash and native check for the exact candidate being reviewed; do not infer hardware ratings from a rendered population.
The three additional revisions are v16, v17, v18. They are engineering studies; saved CAD and renders do not release the hardware. The latest candidate is described below. Older baseline notes above remain historical.
0323ccda35106d6991ba227f058cddae00bc364d60a563943198f937adb1b7ac.Applicable protection, current-path, thermal, pinout, cable access and physical tests remain open wherever the linked board record has not verified them. A zero native-error count does not close those gates.