Passively expose all ten Y-socket contacts on individually accessible 3.5 mm screw terminals.
Baseline documentation snapshot: 2026-10-11, before the requested connector/protection/usability revision program. New revision features require their own reviewed source and qualification evidence.
This page documents an unqualified engineering study, not a released or tested product. Saved CAD, renders and automated checks do not establish a safe assembly, compatible cable, firmware support or a usable current rating.
The retained design record states:
Current inspection prototype:46×32 mm passive Y terminal/chain adapter, same-host populated Qwiic, and seven conditional LRC LESD8D3.3CAT5G SOD-882 shunts. This supersedes the historical unprotected draft below; it does not add level shifting, buffering or a controller. Selected package and component decisions, comparison and parent review are authoritative for the retained CAD. Both Smoothieboard BOMs were reviewed; the V2 TVS family is conditional, its generic0402 label is not the adopted SOD-882 land pattern, and no stock quantity or exact connector reuse is established.
Board-specific qualification limits: v17 ERC/geometry/parity0,fiveopens,no ignored categories;seven conservative mask contacts,host current/cutlinks/ESD/mating/assembly/physical unsigned.
The table below uses the repository-canonical connector rule: pin 1 is +3.3 V, pin 2 is +5 V, and pin 10 is GND. Do not release a schematic from this table until it is reconciled pin-by-pin with the current V2 Prime connector implementation; current web documentation presents a conflicting ordering.
| Pin | Function | Design note |
|---|---|---|
| 1 | +3.3 V | Canonical fixed rail. |
| 2 | +5 V | Canonical fixed rail. |
| 3 | GPIO! | Board mapping; validate against current V2 hardware before layout. |
| 4 | GPIO | Board mapping; validate against current V2 hardware before layout. |
| 5 | GPIO | Board mapping; validate against current V2 hardware before layout. |
| 6 | GPIO | Board mapping; validate against current V2 hardware before layout. |
| 7 | GPIO | Board mapping; validate against current V2 hardware before layout. |
| 8 | GPIO | Board mapping; validate against current V2 hardware before layout. |
| 9 | GPIO | Board mapping; validate against current V2 hardware before layout. |
| 10 | GND | Canonical fixed rail. |
Power off before connecting or changing jumpers. Verify pin 1, signal direction, supply voltage and ground at both ends of every cable. A mechanically fitting connector is not proof of electrical compatibility. If a host pin mapping or current allocation remains unresolved in the design record, do not connect the board until it is resolved.
The following are specification requirements or study assumptions; they are not measured operating ratings. A newer selected-revision note takes precedence over historical draft options.
The design describes the following protection intent. Check the selected schematic and remaining qualification gates before relying on it:
Use recessed terminals, clear polarity marking, keyed Gadgeteer connectors, and copper spacing that prevents solder bridges between rails.
See current review. Retain passive terminal access and populated same-bus Qwiic; seven conditional V2 LRC SOD882 shunts already added v12. No spare active function or exact connector substitution justified;retain v17,no successor. Current selected v17; retained native/stock/physical qualification limits remain explicit.
Use the configuration and firmware contract for the exact selected revision. Do not copy another module’s socket assignments or assume that an unused pin is available. First-article work must verify source selection, reset/unplug behavior, cable orientation and the actual load or sensor interface before normal operation.
The following are requirements for the next design iterations; this page does not claim they are already fitted:
Documentation route: smoothieware.org/extensions/raw-pins-screw-terminal-breakout.
The 2026-10-11 upgrade program has saved additional candidates v18, v19, v20. These studies preserve the historical design described above. Their connector, LED, mechanical and protection changes are revision-specific and remain unqualified.
See the per-board changes, failures and remaining work and mandatory family specification. Use the source hash and native check for the exact candidate being reviewed; do not infer hardware ratings from a rendered population.
The three additional revisions are v18, v19, v20. They are engineering studies; saved CAD and renders do not release the hardware. The latest candidate is described below. Older baseline notes above remain historical.
f7c058285b7cada26ff504c03d159c9804f7340c9b52ef5e23ee30a0d5a81d6f.PinHeader_1x04_P2.54mm_Vertical. Fit only the selected population; check its pin map and voltage in the design record.Applicable protection, current-path, thermal, pinout, cable access and physical tests remain open wherever the linked board record has not verified them. A zero native-error count does not close those gates.
Protected source v23; current PCB SHA-256 6495237a6bcae001f61aa7bd6edd3a686ec629eea3c57aaa059381a7d1db6b46. Fresh checks: zero enabled PCB errors/opens/parity and ERC errors; 23 PCB warnings. Electrical geometry, project rules and 94 historical files unchanged. Verified 22 model entries, 17 exports and 12 current population views, all inspected. Full documentation URL readable. Inherited 23 PCB library warnings and 68 schematic library/link warnings remain; exact libraries preserved Inherited native warnings and enabled-rule exclusions remain explicit Physical/thermal/current/connector-fit qualification open No priced or area savings established by annotation candidate.
The initial v24 registration was withdrawn after comparing diagnostics with the zero-warning v23 baseline: omitted native-source libraries caused23 PCB and68 schematic warnings. Exact authored dependencies restored; final fresh checks and population exports pending. Initial record retained as failed review history, not accepted status.
Protected source v23; current PCB SHA-256 6495237a6bcae001f61aa7bd6edd3a686ec629eea3c57aaa059381a7d1db6b46. Fresh checks: zero enabled PCB errors/opens/parity and ERC errors; 0 PCB warnings. Electrical geometry, project rules and 94 historical files unchanged. Verified 22 model entries, 17 exports and 12 current population views, all inspected. Full documentation URL readable. Exact authored native-source dependencies restored; initial warning regression withdrawn and retained as review history Inherited native warnings and enabled-rule exclusions remain explicit Physical/thermal/current/connector-fit qualification open No priced or area savings established by annotation candidate.