Expose one canonical Y-socket’s ten contacts on a straight 2.54 mm header with one-to-one mapping and continuous GND. The v11 study adds seven bidirectional transient shunts on GPIO pins3–9.
Baseline documentation snapshot: 2026-10-11, before the requested connector/protection/usability revision program. New revision features require their own reviewed source and qualification evidence.
This page documents an unqualified engineering study, not a released or tested product. Saved CAD, renders and automated checks do not establish a safe assembly, compatible cable, firmware support or a usable current rating.
Board-specific qualification limits: v11 CAD checks are zero but system ESD/host survival, actual mating, assembly, cut-link states and checklist signoff remain open.
The table below uses the repository-canonical connector rule: pin 1 is +3.3 V, pin 2 is +5 V, and pin 10 is GND. The retained exact native-host netlist extract confirms J32-J40 pins1=/3V3_LIMIT,2=/5V_LIMIT,10=GND, consistent with the canonical map. Actual host/cable orientation remains physically unqualified.
| Pin | Function | Design note |
|---|---|---|
| 1 | +3.3 V | Canonical fixed rail. |
| 2 | +5 V | Canonical fixed rail. |
| 3 | GPIO! | Board mapping; validate against current V2 hardware before layout. |
| 4 | GPIO | Board mapping; validate against current V2 hardware before layout. |
| 5 | GPIO | Board mapping; validate against current V2 hardware before layout. |
| 6 | GPIO | Board mapping; validate against current V2 hardware before layout. |
| 7 | GPIO | Board mapping; validate against current V2 hardware before layout. |
| 8 | GPIO | Board mapping; validate against current V2 hardware before layout. |
| 9 | GPIO | Board mapping; validate against current V2 hardware before layout. |
| 10 | GND | Canonical fixed rail. |
Power off before connecting or changing jumpers. Verify pin 1, signal direction, supply voltage and ground at both ends of every cable. A mechanically fitting connector is not proof of electrical compatibility. If a host pin mapping or current allocation remains unresolved in the design record, do not connect the board until it is resolved.
The following are specification requirements or study assumptions; they are not measured operating ratings. A newer selected-revision note takes precedence over historical draft options.
The design describes the following protection intent. Check the selected schematic and remaining qualification gates before relying on it:
Keying and pin-1 markings document mating intent; they do not establish ESD or miswire protection. ExposedGPIO lacks protection and no source-backed system exception exists. Any remedy requires actual host/receiver/exposure limits and a reviewed contract; do not choose arbitrary clamps.
See current review. Keep passive one-to-one adapter and exact keyed connectors; retain seven conditional V2 LRC SOD-882 shunts already in v11; no further revision. Current selected v11; retained native/stock/physical qualification limits remain explicit.
Use the configuration and firmware contract for the exact selected revision. Do not copy another module’s socket assignments or assume that an unused pin is available. First-article work must verify source selection, reset/unplug behavior, cable orientation and the actual load or sensor interface before normal operation.
The following are requirements for the next design iterations; this page does not claim they are already fitted:
Documentation route: smoothieware.org/extensions/raw-pins-breakout.
The 2026-10-11 upgrade program has saved additional candidates v12, v13, v14. These studies preserve the historical design described above. Their connector, LED, mechanical and protection changes are revision-specific and remain unqualified.
See the per-board changes, failures and remaining work and mandatory family specification. Use the source hash and native check for the exact candidate being reviewed; do not infer hardware ratings from a rendered population.
The three additional revisions are v12, v13, v14. They are engineering studies; saved CAD and renders do not release the hardware. The latest candidate is described below. Older baseline notes above remain historical.
549a1e03471a84ac629584d24ff20ae573ad3d160b4e8a976890c446d67ba241.Applicable protection, current-path, thermal, pinout, cable access and physical tests remain open wherever the linked board record has not verified them. A zero native-error count does not close those gates.
This saved engineering candidate updates revision labels and annotation styling while preserving the electrical geometry, schematic, project rules and baseline files. Independent current checks find zero enabled board errors, open connections, parity errors and schematic-rule errors; 0 board warnings remain. Six current normal-population views and source-bound manufacturing/model hashes were verified for this board.
The documentation URL is still absent from the board. The automatic placement search found no readable clear area while retaining existing annotations; deliberate label reflow remains to be tried. This requirement is pending, and the revision does not establish assembly or fabrication qualification, area savings or priced savings.
1945f91b08a2d172178e9a79d10fa38c00cda04ff3cce7590c19a8ebc052c5a2.Earlier revision contracts and readbacks on this page remain historical. Physical connector fit, mounting, fault, current and thermal qualification remain open where applicable.