Expose 12 output and 5 input machine-control signals on a legacy DB25 interface, isolated and buffered from Smoothieboard V2.
Native v21, derived from retained v20, replaces nine dual optocoupler packages and their LED resistors with three ISO7760DWR digital isolators. Twelve outputs and five inputs, host/field domains, buffered signal polarity and disabled-output defaults remain. The four-layer outline remains 120 × 140 mm; native footprint count falls from 256 to 213. The non-F high-default isolators are intentional.
The retained candidate has zero native electrical-rule, full-track design-rule, connectivity, schematic/PCB parity and component-contract findings. Its four copper fabrication layers preserve the center isolation gap. Fresh populated/bare views and candidate manufacturing exports accompany the engineering record. These checks do not establish machine safety: human run permission, host power, actual DB25 connector/harness, thermal, assembly and physical isolation remain unqualified. No firmware was changed. All older revisions remain available; the development snapshot below is historical.
Baseline documentation snapshot: 2026-10-11, before the requested connector/protection/usability revision program. New revision features require their own reviewed source and qualification evidence.
This page documents an unqualified engineering study, not a released or tested product. Saved CAD, renders and automated checks do not establish a safe assembly, compatible cable, firmware support or a usable current rating.
Board-specific qualification limits: v17 native checks are zero but only 4/39 bypass pairs meet package limits; 28 inherited via-drill/SMD and 12 annular-only assembly contacts remain, and checklist/physical gates are unsigned.
The following is the repository-canonical 10-pin mapping for the selected/candidate socket arrangement. Pin 1 is +3.3 V, pin 2 is +5 V, and pin 10 is GND. Current V2 Prime documentation describes a different physical rail placement; do not create footprints, cables, or copper until the real target hardware is inspected and this discrepancy is closed.
| Pin | Function |
|---|---|
| 1 | Port supply: +3.3 V on each socket |
| 2 | Port supply: +5 V on each socket |
| 3 | Y1 GPIO1 / Y2 GPIO8 / X GPIO15 |
| 4 | Y1 GPIO2 / Y2 GPIO9 / X GPIO16 |
| 5 | Y1 GPIO3 / Y2 GPIO10 / X GPIO17 |
| 6 | Y1 GPIO4 / Y2 GPIO11 / X unused |
| 7 | Y1 GPIO5 / Y2 GPIO12 / X unused |
| 8 | Y1 GPIO6 / Y2 GPIO13 / X unused |
| 9 | Y1 GPIO7 / Y2 GPIO14 / X unused |
| 10 | Common V2-side GND on each socket |
Power off before connecting or changing jumpers. Verify pin 1, signal direction, supply voltage and ground at both ends of every cable. A mechanically fitting connector is not proof of electrical compatibility. If a host pin mapping or current allocation remains unresolved in the design record, do not connect the board until it is resolved.
The following are specification requirements or study assumptions; they are not measured operating ratings. A newer selected-revision note takes precedence over historical draft options.
The design describes the following protection intent. Check the selected schematic and remaining qualification gates before relying on it:
Add DB25 ESD, input current limiting, isolated-domain spacing, output-enable pull-downs and short-circuit-aware buffers. Bond or RC-couple the connector shell only according to the chassis plan.
See current review. Retain optocoupler/buffer design; defer ISO7760 as a new architecture, not a drop-in. Conditional V1 0603 resistor families only; no new revision. Current selected v17; retained native/stock/physical qualification limits remain explicit.
Use the configuration and firmware contract for the exact selected revision. Do not copy another module’s socket assignments or assume that an unused pin is available. First-article work must verify source selection, reset/unplug behavior, cable orientation and the actual load or sensor interface before normal operation.
The following are requirements for the next design iterations; this page does not claim they are already fitted:
Documentation route: smoothieware.org/extensions/parallel-port-breakout.
The 2026-10-11 upgrade program has saved additional candidates v18, v19, v20. These studies preserve the historical design described above. Their connector, LED, mechanical and protection changes are revision-specific and remain unqualified.
See the per-board changes, failures and remaining work and mandatory family specification. Use the source hash and native check for the exact candidate being reviewed; do not infer hardware ratings from a rendered population.
The three additional revisions are v18, v19, v20. They are engineering studies; saved CAD and renders do not release the hardware. The latest candidate is described below. Older baseline notes above remain historical.
284b430acaf78a4715993d1324960ecef40e41263f1afd896fcd1318ba1ba894.Applicable protection, current-path, thermal, pinout, cable access and physical tests remain open wherever the linked board record has not verified them. A zero native-error count does not close those gates.
Protected source v21; current PCB SHA-256 2753ab9f5785c3f6db221b1a04c08cd505818b57094c1e4d2ca4213d3984c70a. Fresh checks: zero enabled PCB errors/opens/parity and ERC errors; 0 PCB warnings. Electrical geometry, project rules and 57 historical files unchanged. Verified 198 model entries, 19 exports and 6 current population views, all inspected. Full documentation URL readable. Protective-interface and current limits remain provisional Inherited native warnings and enabled-rule exclusions remain explicit Physical/thermal/current/connector-fit qualification open No priced or area savings established by annotation candidate.