Adapt a named Papilio FPGA board and wing connector revision to one or more compatible Gadgeteer interfaces.
Baseline documentation snapshot: 2026-10-11, before the requested connector/protection/usability revision program. New revision features require their own reviewed source and qualification evidence.
This page documents an unqualified engineering study, not a released or tested product. Saved CAD, renders and automated checks do not establish a safe assembly, compatible cable, firmware support or a usable current rating.
Board-specific qualification limits: Native checks zero and rear silkscreen collision corrected; independent final review, exact connector/cable fit, physical/ESD/thermal qualification remain unsigned.
The following is the repository-canonical 10-pin mapping for the selected/candidate socket arrangement. Pin 1 is +3.3 V, pin 2 is +5 V, and pin 10 is GND. Current V2 Prime documentation describes a different physical rail placement; do not create footprints, cables, or copper until the real target hardware is inspected and this discrepancy is closed.
| Pin | Function |
|---|---|
| 1 | +3.3 V canonical; destination TBD |
| 2 | +5 V canonical; destination TBD |
| 3 | TBD signal 1 |
| 4 | TBD signal 2 |
| 5 | TBD signal 3 |
| 6 | TBD signal 4 |
| 7 | TBD signal 5 |
| 8 | TBD signal 6 |
| 9 | TBD signal 7 |
| 10 | GND; destination TBD |
Power off before connecting or changing jumpers. Verify pin 1, signal direction, supply voltage and ground at both ends of every cable. A mechanically fitting connector is not proof of electrical compatibility. If a host pin mapping or current allocation remains unresolved in the design record, do not connect the board until it is resolved.
The following are specification requirements or study assumptions; they are not measured operating ratings. A newer selected-revision note takes precedence over historical draft options.
The design describes the following protection intent. Check the selected schematic and remaining qualification gates before relying on it:
Default all power-link jumpers open; add Ioff-capable buffers if domains can power independently and ESD where connectors are externally accessible.
See current review. Retain passive interface and seven 470Ω 1% series resistors; no exact stock resistor match; no IC addition or active translator justified; v13 retained. Current selected v13; retained native/stock/physical qualification limits remain explicit.
Use the configuration and firmware contract for the exact selected revision. Do not copy another module’s socket assignments or assume that an unused pin is available. First-article work must verify source selection, reset/unplug behavior, cable orientation and the actual load or sensor interface before normal operation.
The following are requirements for the next design iterations; this page does not claim they are already fitted:
Documentation route: smoothieware.org/extensions/papilio-adapter.
The 2026-10-11 upgrade program has saved additional candidates v14, v15, v16. These studies preserve the historical design described above. Their connector, LED, mechanical and protection changes are revision-specific and remain unqualified.
See the per-board changes, failures and remaining work and mandatory family specification. Use the source hash and native check for the exact candidate being reviewed; do not infer hardware ratings from a rendered population.
The three additional revisions are v14, v15, v16. They are engineering studies; saved CAD and renders do not release the hardware. The latest candidate is described below. Older baseline notes above remain historical.
9b375e4f67a3edce2bcc5896857b5b9ea7ed249485a6b473a2e496d6073d379a.Applicable protection, current-path, thermal, pinout, cable access and physical tests remain open wherever the linked board record has not verified them. A zero native-error count does not close those gates.
Protected source v16; current PCB SHA-256 9ede7353b510781fbfe36d3ba05d55ca7aaface6d9cdb2a0fa97cf4450a48c91. Fresh checks: zero enabled PCB errors/opens/parity and ERC errors; 3 PCB warnings. Electrical geometry, project rules and 36 historical files unchanged. Verified 10 model entries, 17 exports and 6 current population views, all inspected. Full documentation URL readable. Five inherited ignored PCB categories remain explicit; assembly and provisional rail limits unqualified Inherited native warnings and enabled-rule exclusions remain explicit Physical/thermal/current/connector-fit qualification open No priced or area savings established by annotation candidate.