Provide galvanic isolation for a deliberately defined set of seven extension signals; arbitrary reversible Gadgeteer isolation is not electrically well-defined.
Baseline documentation snapshot: 2026-10-11, before the requested connector/protection/usability revision program. New revision features require their own reviewed source and qualification evidence.
This page documents an unqualified engineering study, not a released or tested product. Saved CAD, renders and automated checks do not establish a safe assembly, compatible cable, firmware support or a usable current rating.
Board-specific qualification limits: Native checks clean per v12 disposition; independent final review and physical isolation/timing/return-path and full checklist qualification remain open.
The table below uses the repository-canonical connector rule: pin 1 is +3.3 V, pin 2 is +5 V, and pin 10 is GND. Do not release a schematic from this table until it is reconciled pin-by-pin with the current V2 Prime connector implementation; current web documentation presents a conflicting ordering.
| Pin | Function | Design note |
|---|---|---|
| 1 | +3.3 V | Canonical fixed rail. |
| 2 | +5 V | Canonical fixed rail. |
| 3 | PROFILE_SIG1 | Board mapping; validate against current V2 hardware before layout. |
| 4 | PROFILE_SIG2 | Board mapping; validate against current V2 hardware before layout. |
| 5 | PROFILE_SIG3 | Board mapping; validate against current V2 hardware before layout. |
| 6 | PROFILE_SIG4 | Board mapping; validate against current V2 hardware before layout. |
| 7 | PROFILE_SIG5 | Board mapping; validate against current V2 hardware before layout. |
| 8 | PROFILE_SIG6 | Board mapping; validate against current V2 hardware before layout. |
| 9 | PROFILE_SIG7 | Board mapping; validate against current V2 hardware before layout. |
| 10 | GND | Canonical fixed rail. |
Power off before connecting or changing jumpers. Verify pin 1, signal direction, supply voltage and ground at both ends of every cable. A mechanically fitting connector is not proof of electrical compatibility. If a host pin mapping or current allocation remains unresolved in the design record, do not connect the board until it is resolved.
The following are specification requirements or study assumptions; they are not measured operating ratings. A newer selected-revision note takes precedence over historical draft options.
The design describes the following protection intent. Check the selected schematic and remaining qualification gates before relying on it:
Certified isolation barrier/slot, ESD on cable sides, current limiting, no back-power through I/O, and standards-derived creepage/clearance.
See current review. Retain ISOW7741+ISO7730 and selected DBVR protection package; use only qualified V1 support passives, reject unverified 0402/package swaps; no new revision. Current selected v12; retained native/stock/physical qualification limits remain explicit.
Use the configuration and firmware contract for the exact selected revision. Do not copy another module’s socket assignments or assume that an unused pin is available. First-article work must verify source selection, reset/unplug behavior, cable orientation and the actual load or sensor interface before normal operation.
The following are requirements for the next design iterations; this page does not claim they are already fitted:
Documentation route: smoothieware.org/extensions/opto-isolation-pass-through-board.
The 2026-10-11 upgrade program has saved additional candidates v13, v14, v15. These studies preserve the historical design described above. Their connector, LED, mechanical and protection changes are revision-specific and remain unqualified.
See the per-board changes, failures and remaining work and mandatory family specification. Use the source hash and native check for the exact candidate being reviewed; do not infer hardware ratings from a rendered population.
The three additional revisions are v13, v14, v15. They are engineering studies; saved CAD and renders do not release the hardware. The latest candidate is described below. Older baseline notes above remain historical.
1391ea5f525ae65a7e3ff293d9e079a63f96d6afb677f534af536b5a95fffa9c.Applicable protection, current-path, thermal, pinout, cable access and physical tests remain open wherever the linked board record has not verified them. A zero native-error count does not close those gates.
Protected source v19; current PCB SHA-256 c46abee9f37e1049f40615f40ed71a64b483364132e17026c525ac9dd170f0d2. Fresh checks: zero enabled errors/opens/parity/ERC findings; 0 PCB warnings. Electrical geometry, project rules and 73 historical files unchanged. Verified 32 model entries, 17 exports and 6 current population views, all inspected. Full documentation URL readable. Heavy title font pending; readable uppercase stroke font retained Inherited native warnings and enabled-rule exclusions remain explicit Physical/thermal/current/connector-fit qualification open No priced or area savings established by annotation candidate.