Provide seven low-current GPIO debug indicators without imposing excessive source current on V2 pins.
Baseline documentation snapshot: 2026-10-11, before the requested connector/protection/usability revision program. New revision features require their own reviewed source and qualification evidence.
This page documents an unqualified engineering study, not a released or tested product. Saved CAD, renders and automated checks do not establish a safe assembly, compatible cable, firmware support or a usable current rating.
Board-specific qualification limits: v10 native checks clean but checklist only 2/132 pass; exact stock MPN/quantity/power/ambient rating, brightness, cable polarity and host budget remain unqualified.
Power off before connecting or changing jumpers. Verify pin 1, signal direction, supply voltage and ground at both ends of every cable. A mechanically fitting connector is not proof of electrical compatibility. If a host pin mapping or current allocation remains unresolved in the design record, do not connect the board until it is resolved.
The following are specification requirements or study assumptions; they are not measured operating ratings. A newer selected-revision note takes precedence over historical draft options.
See current review. Retain v10/direct GPIO indicators and existing conditional V1 2.2k resistor/bypass reuse; eight resistor identities remain UNCONFIRMED. No successor; native/checklist/host/stock/physical limits remain explicit.
Use the configuration and firmware contract for the exact selected revision. Do not copy another module’s socket assignments or assume that an unused pin is available. First-article work must verify source selection, reset/unplug behavior, cable orientation and the actual load or sensor interface before normal operation.
The following are requirements for the next design iterations; this page does not claim they are already fitted:
Documentation route: smoothieware.org/extensions/led-breakout.
The 2026-10-11 upgrade program has saved additional candidates v11, v12, v13. These studies preserve the historical design described above. Their connector, LED, mechanical and protection changes are revision-specific and remain unqualified.
See the per-board changes, failures and remaining work and mandatory family specification. Use the source hash and native check for the exact candidate being reviewed; do not infer hardware ratings from a rendered population.
The three additional revisions are v11, v12, v13. They are engineering studies; saved CAD and renders do not release the hardware. The latest candidate is described below. Older baseline notes above remain historical.
5accdbc249221159ab23c19efa1c9cf7ba4ed41273fd67a019c053af407a9193.Applicable protection, current-path, thermal, pinout, cable access and physical tests remain open wherever the linked board record has not verified them. A zero native-error count does not close those gates.
Protected source v17; current PCB SHA-256 a2e75ef1e45973aec2307918e1add6d66627c3c44fe7778ddf69913fa0f1af16. Fresh checks: zero enabled PCB errors/opens/parity and ERC errors; 56 PCB warnings. Electrical geometry, project rules and 67 historical files unchanged. Verified 19 model entries, 17 exports and 6 current population views, all inspected. Full documentation URL readable. Inherited instruction/reference overlaps remain Inherited native warnings and enabled-rule exclusions remain explicit Physical/thermal/current/connector-fit qualification open No priced or area savings established by annotation candidate.