Historical record only for a discontinued Intel Edison carrier concept.
Second-round candidate accepted for engineering review — 2026-10-13. The v20 package has current source-bound native checks, complete resolving model references, exports and six inspected normal-population/bare views. Newly recovered purple bodies are dimensioned principal-body prisms with contacts, voids and mating features omitted; they are not manufacturer or fit models. Inherited native findings and label crowding remain documented in the board work record. Hardware, electrical and mechanical qualification remain open; no fabrication release or priced saving is claimed.
Baseline documentation snapshot: 2026-10-11, before the requested connector/protection/usability revision program. New revision features require their own reviewed source and qualification evidence.
This page documents an unqualified engineering study, not a released or tested product. Saved CAD, renders and automated checks do not establish a safe assembly, compatible cable, firmware support or a usable current rating.
Board-specific qualification limits: v12/33 purchased/32 identity strings match/1 stock blank;71 selected/944 historical hashes;DRC1/connector peak/host/reset/USB/physical open.
The canonical repository connector contract is pin 1 = +3.3 V, pin 2 = +5 V, pin 10 = GND. Current Smoothie V2 Prime web material appears to describe a conflicting header assignment; the physical target header must be continuity-checked against its authoritative schematic before KiCad release. The table below expresses design intent against the repository’s canonical contract, not proof of the live board pinout.
| Pin | Canonical role | Assigned function |
|---|---|---|
| 1 | +3.3V | +3.3 V rail |
| 2 | +5V | +5 V rail |
| 3 | GPIO! / type-specific | N/C — inactive |
| 4 | type-specific | N/C — inactive |
| 5 | type-specific | N/C — inactive |
| 6 | type-specific | N/C — inactive |
| 7 | type-specific | N/C — inactive |
| 8 | type-specific | N/C — inactive |
| 9 | type-specific | N/C — inactive |
| 10 | GND | Ground |
Power off before connecting or changing jumpers. Verify pin 1, signal direction, supply voltage and ground at both ends of every cable. A mechanically fitting connector is not proof of electrical compatibility. If a host pin mapping or current allocation remains unresolved in the design record, do not connect the board until it is resolved.
The following are specification requirements or study assumptions; they are not measured operating ratings. A newer selected-revision note takes precedence over historical draft options.
The design describes the following protection intent. Check the selected schematic and remaining qualification gates before relying on it:
Current v12 review covers52records/33 purchased components and existing V1 R5 discharge class. Retain dedicated power/translator,no successor. One MOD1 DRC finding,connector peak/host allowance,procurement/reset/USB/stackup/physical gates remain open.
Use the configuration and firmware contract for the exact selected revision. Do not copy another module’s socket assignments or assume that an unused pin is available. First-article work must verify source selection, reset/unplug behavior, cable orientation and the actual load or sensor interface before normal operation.
The following are requirements for the next design iterations; this page does not claim they are already fitted:
Documentation route: smoothieware.org/extensions/intel-edison-breakout.
The 2026-10-11 upgrade program has saved additional candidates v13, v14, v15. These studies preserve the historical design described above. Their connector, LED, mechanical and protection changes are revision-specific and remain unqualified.
See the per-board changes, failures and remaining work and mandatory family specification. Use the source hash and native check for the exact candidate being reviewed; do not infer hardware ratings from a rendered population.
The three additional revisions are v13, v14, v15. They are engineering studies; saved CAD and renders do not release the hardware. The latest candidate is described below. Older baseline notes above remain historical.
a9d668dc4ef61ece34c696398bb00c35dfa2be73dc42c846280fa606968a970f.Applicable protection, current-path, thermal, pinout, cable access and physical tests remain open wherever the linked board record has not verified them. A zero native-error count does not close those gates.