Provide a magnetic endstop module with a Signal/Ground/5 V connection and explicit normal and fault-state behavior. The historical v13 design remains unqualified; the annotation-only v18 candidate below does not establish a qualified machine limit.
Baseline documentation snapshot: 2026-10-11, before the requested connector/protection/usability revision program. New revision features require their own reviewed source and qualification evidence.
This page documents an unqualified engineering study, not a released or tested product. Saved CAD, renders and automated checks do not establish a safe assembly, compatible cable, firmware support or a usable current rating.
Board-specific qualification limits: v13/10 purchased identities/15records/128 selected/1243 historical hashes match;retained native0;host/magnet/fault/physical open.
The PCB has no Gadgeteer socket: J1 is pin 1 SIGNAL_OUT, pin 2 GND, pin 3 +5 V. The table below is the repository-canonical host-side X adapter mapping only. Current V2 Prime documentation describes a different physical rail placement; do not release an adapter cable or claim physical compatibility until the real target is inspected and this discrepancy is closed.
| Pin | Function |
|---|---|
| 1 | +3.3 V host logic |
| 2 | +5 V sensor supply candidate |
| 3 | HALL_ENDSTOP |
| 4 | Unused |
| 5 | Unused |
| 6 | Unused |
| 7 | Unused |
| 8 | Unused |
| 9 | Unused |
| 10 | GND |
Power off before connecting or changing jumpers. Verify pin 1, signal direction, supply voltage and ground at both ends of every cable. A mechanically fitting connector is not proof of electrical compatibility. If a host pin mapping or current allocation remains unresolved in the design record, do not connect the board until it is resolved.
The following are specification requirements or study assumptions; they are not measured operating ratings. A newer selected-revision note takes precedence over historical draft options.
The design describes the following protection intent. Check the selected schematic and remaining qualification gates before relying on it:
The retained circuit has connector signal ESD (D1), C1 supply bypass and R2/C2 output filtering; the signal high level is supplied only by the 3.3 V host. It has no supply fuse, reverse-supply stage or supply TVS. Do not claim 24 V miswire tolerance or safe brownout behavior. R2 is RC1206FR-07330RL, 330 Ω 1%, 0.25 W at 70 °C. A 5.25 V signal short gives an ideal-source upper bound of 84.37 mW at 326.7 Ω; its manufacturer linear derating gives 205.88 mW at 85 °C. This is a calculated margin, with fault duration and actual thermal behavior unqualified.
Selected v13 review covers15records/10 purchased identities. Retain DRV5033AJ and existing BSS138BK/1206 fault-resistor upgrades;earlier2N7002/0603 stock study is historical. Conditional V1 bypass/pulls only,no successor;host/magnet/fault/thermal/physical gates remain.
Use the configuration and firmware contract for the exact selected revision. Do not copy another module’s socket assignments or assume that an unused pin is available. First-article work must verify source selection, reset/unplug behavior, cable orientation and the actual load or sensor interface before normal operation.
The following are requirements for the next design iterations; this page does not claim they are already fitted:
Documentation route: smoothieware.org/extensions/hall-endstop-breakout.
The 2026-10-11 upgrade program has saved additional candidates v14, v15, v16. These studies preserve the historical design described above. Their connector, LED, mechanical and protection changes are revision-specific and remain unqualified.
See the per-board changes, failures and remaining work and mandatory family specification. Use the source hash and native check for the exact candidate being reviewed; do not infer hardware ratings from a rendered population.
The three additional revisions are v14, v15, v16. They are engineering studies; saved CAD and renders do not release the hardware. The historical first-program candidate is described below; second-round v18 results are recorded separately further down.
a2520e37f4d11516d0c7af8b12a7e12bbd5e2a1a6fe2fc2bddf0d25cf1cb9a42.JST_PH_B3B-PH-K_1x03_P2.00mm_Vertical. Fit only the selected population; check its pin map and voltage in the design record.Applicable protection, current-path, thermal, pinout, cable access and physical tests remain open wherever the linked board record has not verified them. A zero native-error count does not close those gates.
Revision titles are corrected. The complete website URL still needs readable clear space; this revision does not claim that requirement is met.
No enabled native design-rule or electrical-rule diagnostics remain. The protected v17 circuit, exact non-text electrical geometry, component placement, outline, schematic and electrical rule settings are unchanged. This is an annotation candidate, with no new components and no area or priced purchasing saving claimed.
All12 populated/bare top, bottom and isometric views across the existing normal and keyed STEMMA-family populations were hash-verified and inspected, with manufacturing exports, BOM and placement files regenerated from the current source. Select the connector and cable by the exact source pin map; matching connector shape does not establish interchangeable pin order or an I²C interface.
Current v18 source, SHA-256 2af85424da054ad77b81d73755e712ebbfe8f022b647018225b5d53e313f8fc5. Board-local second-round changes, ignored rules and remaining work.
Physical assembly, connector fit, actual host wiring, fault-state behavior and sensor qualification remain open. Fabrication release remains false.