Adapt a defined RepRapDiscount Full Graphic Smart Controller revision to Smoothie V2 while actively isolating its non-compliant ST7920 serial interface.
Baseline documentation snapshot: 2026-10-11, before the requested connector/protection/usability revision program. New revision features require their own reviewed source and qualification evidence.
This page documents an unqualified engineering study, not a released or tested product. Saved CAD, renders and automated checks do not establish a safe assembly, compatible cable, firmware support or a usable current rating.
Board-specific qualification limits: v10/37 purchased identities/48records/114 selected/456 historical hashes match;retained native0;panel/shared-rail/STEP/physical open.
The table below uses the repository-canonical connector rule: pin 1 is +3.3 V, pin 2 is +5 V, and pin 10 is GND. Do not release a schematic from this table until it is reconciled pin-by-pin with the current V2 Prime connector implementation; current web documentation presents a conflicting ordering.
| Pin | Function | Design note |
|---|---|---|
| 1 | +3.3 V | Canonical fixed rail. |
| 2 | +5 V | Canonical fixed rail. |
| 3 | S:GPIO!/Y:GPIO1 | Board mapping; validate against current V2 hardware before layout. |
| 4 | S:GPIO/Y:GPIO2 | Board mapping; validate against current V2 hardware before layout. |
| 5 | S:GPIO/Y:GPIO3 | Board mapping; validate against current V2 hardware before layout. |
| 6 | S:CS/Y:GPIO4 | Board mapping; validate against current V2 hardware before layout. |
| 7 | S:MOSI/Y:GPIO5 | Board mapping; validate against current V2 hardware before layout. |
| 8 | S:MISO/Y:GPIO6 | Board mapping; validate against current V2 hardware before layout. |
| 9 | S:SCK/Y:GPIO7 | Board mapping; validate against current V2 hardware before layout. |
| 10 | GND | Canonical fixed rail. |
Power off before connecting or changing jumpers. Verify pin 1, signal direction, supply voltage and ground at both ends of every cable. A mechanically fitting connector is not proof of electrical compatibility. If a host pin mapping or current allocation remains unresolved in the design record, do not connect the board until it is resolved.
The following are specification requirements or study assumptions; they are not measured operating ratings. A newer selected-revision note takes precedence over historical draft options.
The design describes the following protection intent. Check the selected schematic and remaining qualification gates before relying on it:
IDC keying, ESD on external panel cable, power-off isolation, current limiting for backlight, and no backfeed from panel SD.
Current v10 review covers48records/37 purchased identities;both exact V2 DCK migrations already implemented. Retain panel gating/isolation and conditional V1 bypass,no successor. Panel/host/shared rail/timing/STEP/physical gates remain open;v06 proposal is historical.
Use the configuration and firmware contract for the exact selected revision. Do not copy another module’s socket assignments or assume that an unused pin is available. First-article work must verify source selection, reset/unplug behavior, cable orientation and the actual load or sensor interface before normal operation.
The following are requirements for the next design iterations; this page does not claim they are already fitted:
Documentation route: smoothieware.org/extensions/glcd-breakout.
The 2026-10-11 upgrade program has saved additional candidates v11, v12, v13. These studies preserve the historical design described above. Their connector, LED, mechanical and protection changes are revision-specific and remain unqualified.
See the per-board changes, failures and remaining work and mandatory family specification. Use the source hash and native check for the exact candidate being reviewed; do not infer hardware ratings from a rendered population.
The three additional revisions are v11, v12, v13. They are engineering studies; saved CAD and renders do not release the hardware. The latest candidate is described below. Older baseline notes above remain historical.
1e10d2c6becbc56d9d4afccdbe80e7584b3fe689f56d8062a4f70f6e985d9143.Applicable protection, current-path, thermal, pinout, cable access and physical tests remain open wherever the linked board record has not verified them. A zero native-error count does not close those gates.
Protected source v13; current PCB SHA-256 e39851257382ad0f58b97aa2fdb96588636cf9ab2c9a67a60f2f9ee55a0d80fc. Fresh checks: zero enabled PCB errors/opens/parity and ERC errors; 3 PCB warnings. Electrical geometry, project rules and 89 historical files unchanged. Verified 72 model entries, 17 exports and 6 current population views, all inspected. Full documentation URL readable. Inherited upper duplicate URL abuts title; lower full URLs readable Inherited native warnings and enabled-rule exclusions remain explicit Physical/thermal/current/connector-fit qualification open No priced or area savings established by annotation candidate.
Engineering revision v15 removes redundant protection on its trusted controller supply. The original 48 × 38 mm outline is restored. Native checks find no errors or open connections; every connector population has six reviewed renders. This remains an unqualified engineering design, not a fabrication release.