The v21 native sources and wiring guide preserve the released v20 isolated CAN circuit, placement and mechanics. The PCB revision label is current and its full documentation URL is retained. The wiring diagrams below describe exact saved pin numbers and default chain jumpers; they do not establish hardware qualification. Fabrication release is false. Native checks and source-bound model/export/render review are recorded in the revision’s can-usability-review.json. Frozen v20 identity-label source drift and its missing auxiliary routed project file remain documented historical exceptions; neither is restored. Teardrop and reference-copper work remain open.
Compatible host CAN controller J1 host socket Isolation J3 field terminal
3.3 V logic supply -------------------> 1 3V3
4.5–5.5 V converter supply -----------> 2 5V ISOW1044
TX-inhibit command ------------------> 3 HOST_SILENT barrier
CAN controller TX -------------------> 4 HOST_TXD || || 3 CANH ---- CANH bus
CAN controller RX <------------------- 5 HOST_RXD || || 2 CANL ---- CANL bus
Host ground -------------------------- 10 GND || || 1 FIELD_GND -- field reference
SILENT high inhibits transmission while reception stays active: the OR gate produces TXD_SAFE = HOST_TXD OR HOST_SILENT. The local SHDN/standby strap is a separate function. Do not connect host ground to FIELD_GND across the isolation barrier. CANH/CANL are communication pins, not machine-power inputs. Firmware, pin mux, CAN controller compatibility, timing and cable orientation require separate verification; this revision adds no firmware.
| Number | J1 host | J2 chain | Default connection |
|---|---|---|---|
| 1 | 3V3 | 3V3 | Direct host-domain power |
| 2 | 5V | 5V | Direct host-domain power |
| 3 | HOST_SILENT | CHAIN_3 | SJ3 open |
| 4 | HOST_TXD | CHAIN_4 | SJ4 open |
| 5 | HOST_RXD | CHAIN_5 | SJ5 open |
| 6 | HOST_6 | CHAIN_6 | SJ6 bridged |
| 7 | HOST_7 | CHAIN_7 | SJ7 bridged |
| 8 | HOST_8 | CHAIN_8 | SJ8 bridged |
| 9 | HOST_9 | CHAIN_9 | SJ9 bridged |
| 10 | GND | GND | Direct host-domain ground |
J2 forwards power/ground and unused pins 6–9. It does not forward the consumed CAN control signals on pins 3–5. A second CAN board cannot simply plug into J2 as another standard CAN C socket. Closing SJ3–5 is not a supported two-transceiver configuration and can connect competing RXD outputs. Downstream power remains subject to the combined source, connector and cable budget.
This is a conditional wiring topology, not a validated shared-power assembly. Each board needs its own compatible controller signals; J2 is not the controller-signal distribution path.
Rated host-domain supply distribution (combined load/drop budget unresolved)
3V3 / 4.5–5.5 V / host GND
+----> board A J1 pins 1 / 2 / 10 <---- controller A pins SILENT/TX/RX
+----> board B J1 pins 1 / 2 / 10 <---- controller B pins SILENT/TX/RX
|| separate isolation barriers ||
Field-domain linear bus (twisted CANH/CANL pair)
End A J3 pin3 CANH ============================= J3 pin3 CANH End B
J3 pin2 CANL ============================= J3 pin2 CANL
J3 pin1 FIELD_GND ------------------------ J3 pin1 FIELD_GND
SJ10 closed: 120 ohm SJ10 closed: 120 ohm
|
Optional interior node:
CANH/CANL/field reference;
SJ10 OPEN, no endpoint termination
Use exactly two 120 ohm terminators, at the two physical ends of the complete linear bus. SJ10 is open by default; interior nodes remain unterminated. Keep stubs short; actual cable, field reference/ground potential, termination, fault envelope and EMC must be engineered for the installation. The 500 kbit/s / 20 m network is a qualification target, not measured operation.
The converter input design uses manufacturer worst-case 211 mA at a 60 ohm dominant bus load and 250 mA pulses per board; the upstream current-limit recommendation is at least 300 mA per board. These figures do not establish the host socket allocation or a safe multi-board budget. Account for every board, other downstream loads, startup, protection behavior, source capacity and cable/contact drops before energization. No extra field-port TVS/bias network is fitted. Host supply, isolation, thermal, current, EMC, firmware, assembly and real network qualification remain open. The generic SOIC model does not certify package fit.
The v20 engineering record and native design adds ISOW1044DFMR isolated CAN alongside the retained common-ground revisions. Host 3.3 V supplies logic; host 4.5–5.5 V supplies the isolated converter. Manufacturer worst-case VDD current is 211 mA at a 60 Ω dominant bus load, with 250 mA pulses; the recommended upstream current-limit target is at least 300 mA. The actual host socket allocation remains unqualified. The 70 × 45 mm candidate is larger than the 40 × 39.5 mm baseline.
A separate transmit-inhibit gate preserves the existing active-high SILENT command while keeping reception active. No firmware is changed, and this is still a native CAN physical interface: the host must provide a compatible CAN controller, driver, timing and bus configuration. The 500 kbit/s / 20 m network remains a qualification target, not measured performance. Native electrical checks pass and fresh renders are retained, but power, thermal behavior, EMC, insulation, assembly and complete network operation remain unqualified. No fabrication or energization approval is granted. The historical snapshot below describes earlier revisions; select the exact revision before wiring.
Gadgeteer-to-CAN physical-interface adapter. CAN 2.0 operation is a design target; the prototype qualification target is 500 kbit/s over a specified 20 m twisted-pair network, not measured performance.
Baseline documentation snapshot: 2026-10-11, before the requested connector/protection/usability revision program. New revision features require their own reviewed source and qualification evidence.
This page documents an unqualified engineering study, not a released or tested product. Saved CAD, renders and automated checks do not establish a safe assembly, compatible cable, firmware support or a usable current rating.
Board-specific qualification limits: v16/9 purchased,7 named MPNs match/2 stock blanks;123 selected/1803 historical hashes;retained native0;host/fault/physical open.
The exact connector orientation, pin mapping and supply ownership must be taken from the selected revision’s schematic and connection specification. Do not infer wiring from the connector shape.
Power off before connecting or changing jumpers. Verify pin 1, signal direction, supply voltage and ground at both ends of every cable. A mechanically fitting connector is not proof of electrical compatibility. If a host pin mapping or current allocation remains unresolved in the design record, do not connect the board until it is resolved.
The following are specification requirements or study assumptions; they are not measured operating ratings. A newer selected-revision note takes precedence over historical draft options.
Current v16 component review retains TCAN330D and existing V1 10k10% stock envelope; all24 records covered,seven named purchasing identities match and R1/R2 remain unidentified stock reels. No successor; host/fault/EMC/physical and unsigned checklist gates remain. Earlier v15 notes are history.
Use the configuration and firmware contract for the exact selected revision. Do not copy another module’s socket assignments or assume that an unused pin is available. First-article work must verify source selection, reset/unplug behavior, cable orientation and the actual load or sensor interface before normal operation.
The following are requirements for the next design iterations; this page does not claim they are already fitted:
Documentation route: smoothieware.org/extensions/gadgeteer-to-can.
The 2026-10-11 upgrade program has saved additional candidates v17, v18, v19. These studies preserve the historical design described above. Their connector, LED, mechanical and protection changes are revision-specific and remain unqualified.
See the per-board changes, failures and remaining work and mandatory family specification. Use the source hash and native check for the exact candidate being reviewed; do not infer hardware ratings from a rendered population.
The three additional revisions are v17, v18, v19. They are engineering studies; saved CAD and renders do not release the hardware. The latest candidate is described below. Older baseline notes above remain historical.
11631fef695cd934603b48994ca1e82913964314b2653eb5ac53e2c433282dae.Applicable protection, current-path, thermal, pinout, cable access and physical tests remain open wherever the linked board record has not verified them. A zero native-error count does not close those gates.
Protected source v20; current PCB SHA-256 06e0655a5f39ab8ec8997d30d5c99ebca10117a1e5a735ae4bf2a73989245575. Fresh checks: zero enabled PCB errors/opens/parity and ERC errors; 0 PCB warnings. Electrical geometry, project rules and 61 historical files unchanged. Verified 20 model entries, 17 exports and 6 current population views, all inspected. Full documentation URL readable. Isolation, shared host-chain power and CAN transceiver behavior remain physically unqualified; no area or cost savings claimed Inherited native warnings and enabled-rule exclusions remain explicit Physical/thermal/current/connector-fit qualification open No priced or area savings established by annotation candidate.