Switch a specified DC load up to a qualified 20 A point in a Fotek-like mechanical format using a MOSFET-based solid-state topology.
Baseline documentation snapshot: 2026-10-11, before the requested connector/protection/usability revision program. New revision features require their own reviewed source and qualification evidence.
This page documents an unqualified engineering study, not a released or tested product. Saved CAD, renders and automated checks do not establish a safe assembly, compatible cable, firmware support or a usable current rating.
Board-specific qualification limits: Native0 retained,no ignored categories;3fail84unsigned,independent/procurement/host/load/surge/physical open.
The following is the repository-canonical 10-pin mapping for the selected/candidate socket arrangement. Pin 1 is +3.3 V, pin 2 is +5 V, and pin 10 is GND. Current V2 Prime documentation describes a different physical rail placement; the retained copper is a study of the canonical mapping. Do not fabricate, connect cables or energize it until the real target hardware is inspected and this discrepancy is closed.
| Pin | Function |
|---|---|
| 1 | +3.3 V logic |
| 2 | Not connected in candidate |
| 3 | DC_ENABLE with pull-down |
| 4 | Not connected in candidate |
| 5 | Unused |
| 6 | Unused |
| 7 | Unused |
| 8 | Unused |
| 9 | Unused |
| 10 | Logic GND |
Power off before connecting or changing jumpers. Verify pin 1, signal direction, supply voltage and ground at both ends of every cable. A mechanically fitting connector is not proof of electrical compatibility. If a host pin mapping or current allocation remains unresolved in the design record, do not connect the board until it is resolved.
The following are specification requirements or study assumptions; they are not measured operating ratings. A newer selected-revision note takes precedence over historical draft options.
The design describes the following protection intent. Check the selected schematic and remaining qualification gates before relying on it:
Retain the candidate fuse, TVS and gate pull-down architecture pending exact-part and load qualification. External freewheel protection is required for inductive loads. A TVS clamp value applies to its stated surge waveform/current; it is not a universal ceiling below the MOSFET limit. Current/thermal diagnostics remain future options, not implemented fault protection.
Exhaustive current review: v14 retains isolated driver/back-to-back FETs and existing2.2kR8 improvement,no successor.20 identities/136own/1728 historical hashes match;generic procurement and host/load/floating-power/surge/physical gates remain unresolved.
Use the configuration and firmware contract for the exact selected revision. Do not copy another module’s socket assignments or assume that an unused pin is available. First-article work must verify source selection, reset/unplug behavior, cable orientation and the actual load or sensor interface before normal operation.
The following are requirements for the next design iterations; this page does not claim they are already fitted:
Documentation route: smoothieware.org/extensions/dc-ssr-board.
The 2026-10-11 upgrade program has saved additional candidates v15, v16, v17. These studies preserve the historical design described above. Their connector, LED, mechanical and protection changes are revision-specific and remain unqualified.
See the per-board changes, failures and remaining work and mandatory family specification. Use the source hash and native check for the exact candidate being reviewed; do not infer hardware ratings from a rendered population.
The three additional revisions are v15, v16, v17. They are engineering studies; saved CAD and renders do not release the hardware. The latest candidate is described below. Older baseline notes above remain historical.
bdf735e50f76f5304eedb655518e8e33da11141dffb4bc6c1f747df1f623436a.Applicable protection, current-path, thermal, pinout, cable access and physical tests remain open wherever the linked board record has not verified them. A zero native-error count does not close those gates.
Protected source v17; current PCB SHA-256 bc54325eec6ee2d9c3d10e323a3ed699e17a98aa267dd60af03eb3acbeb7e197. Fresh checks: zero enabled errors/opens/parity/ERC findings; 2 PCB warnings. Electrical geometry, project rules and 45 historical files unchanged. Verified 20 model entries, 17 exports and 6 current population views, all inspected. Full documentation URL readable. Inherited native warnings and enabled-rule exclusions remain explicit Physical/thermal/current/connector-fit qualification open No priced or area savings established by annotation candidate.