Archival carrier concept connecting a C.H.I.P. computer module to Smoothie through UART and optional external power.
Baseline documentation snapshot: 2026-10-11, before the requested connector/protection/usability revision program. New revision features require their own reviewed source and qualification evidence.
This page documents an unqualified engineering study, not a released or tested product. Saved CAD, renders and automated checks do not establish a safe assembly, compatible cable, firmware support or a usable current rating.
Board-specific qualification limits: Native clean retained;SW area/bypass distance fail,130unsigned, procurement/host/converter/physical open.
The canonical repository connector contract is pin 1 = +3.3 V, pin 2 = +5 V, pin 10 = GND. Current Smoothie V2 Prime web material appears to describe a conflicting header assignment; the physical target header must be continuity-checked against its authoritative schematic before KiCad release. The table below expresses design intent against the repository’s canonical contract, not proof of the live board pinout.
| Pin | Canonical role | Assigned function |
|---|---|---|
| 1 | +3.3V | +3.3 V rail |
| 2 | +5V | +5 V rail |
| 3 | GPIO! / type-specific | GPIO/enable optional |
| 4 | type-specific | Host TX → module RX |
| 5 | type-specific | Host RX ← module TX |
| 6 | type-specific | GPIO/status optional |
| 7 | type-specific | N/C |
| 8 | type-specific | N/C |
| 9 | type-specific | N/C |
| 10 | GND | Ground |
Power off before connecting or changing jumpers. Verify pin 1, signal direction, supply voltage and ground at both ends of every cable. A mechanically fitting connector is not proof of electrical compatibility. If a host pin mapping or current allocation remains unresolved in the design record, do not connect the board until it is resolved.
The following are specification requirements or study assumptions; they are not measured operating ratings. A newer selected-revision note takes precedence over historical draft options.
The design describes the following protection intent. Check the selected schematic and remaining qualification gates before relying on it:
Complete component review: actualv10 retains LMR51430/enabled buffers and existing bypass improvements, no successor. Native clean retained; switch-area/bypass-distance targets and candidate procurement/host/converter/physical gates remain open.
Use the configuration and firmware contract for the exact selected revision. Do not copy another module’s socket assignments or assume that an unused pin is available. First-article work must verify source selection, reset/unplug behavior, cable orientation and the actual load or sensor interface before normal operation.
The following are requirements for the next design iterations; this page does not claim they are already fitted:
Documentation route: smoothieware.org/extensions/chip-breakout-board.
The 2026-10-11 upgrade program has saved additional candidates v11, v12, v13. These studies preserve the historical design described above. Their connector, LED, mechanical and protection changes are revision-specific and remain unqualified.
See the per-board changes, failures and remaining work and mandatory family specification. Use the source hash and native check for the exact candidate being reviewed; do not infer hardware ratings from a rendered population.
The three additional revisions are v11, v12, v13. They are engineering studies; saved CAD and renders do not release the hardware. The latest candidate is described below. Older baseline notes above remain historical.
5647d524c1f7e57c46c6eb550ec1015b465221b52d18e03033b16bf20994470d.Applicable protection, current-path, thermal, pinout, cable access and physical tests remain open wherever the linked board record has not verified them. A zero native-error count does not close those gates.
Protected source v17; current PCB SHA-256 c05d9e89dee760bc0aeefc821da5ee9838fba8e41abedb060f17cac069b130cc. Fresh checks: zero enabled PCB errors/opens/parity and ERC errors; 67 PCB warnings. Electrical geometry, project rules and 96 historical files unchanged. Verified 73 model entries, 17 exports and 6 current population views, all inspected. Full documentation URL readable. Inherited crowded rear annotations and one schematic warning remain; redundant revision note removed to avoid added overlap; CHIP v13.0 ONLY compatibility marking retained Inherited native warnings and enabled-rule exclusions remain explicit Physical/thermal/current/connector-fit qualification open No priced or area savings established by annotation candidate.
The compact carrier returns to 67.8 × 43 mm, rather than the enlarged 67.8 × 53 mm protection-annex outline. All 93 footprints and the complete external-input electronic-fuse, reverse-polarity, overvoltage and fault-indicator circuits are retained. The functional front-side components, connectors and mounting positions remain fixed; protection components occupy the underside. This external input is user wired and must not be treated as a trusted host supply.
Native checks find zero geometry errors, zero unconnected items and zero schematic-parity findings. Silkscreen overlap warnings decrease from 49 to 15 and silkscreen-over-copper warnings from 13 to 5. Remaining library, small-text and footprint-link warnings are inherited. Rendering and export review accompany the saved source; they do not qualify fault thresholds, current capacity, thermal behavior or module/cable insertion.
The underside retains the board title, documentation link, individual test-point labels and labels beside the actual fault LEDs. Detailed wiring tables that would be covered by components are retained on the fabrication layer and here:
| Connection | Wiring |
|---|---|
| U Gadgeteer socket | 1 = 3.3 V; 2 = 5 V; 3 = GPIO; 4 = TX; 5 = RX; 10 = GND |
| C.H.I.P. U13 | 1 and 4 = GND; 2 = CHG-IN 5 V; 5 = 3.3 V |
| U14 | 1 = GND; 3 = TX; 5 = RX |
| SJ1 source selection | Pins 1–2; shipped selection = EXT |
| Fault indicators | DF2 = FAULT; DF5 = OV; DF8 = REV |
| Test points TP1–TP4 | TP1 = GND; TP2 = VIN_PROT; TP3 = BUCK_5V; TP4 = CHIP_5V |
| Test points TP5–TP8 | TP5 = CHIP_3V3; TP6 = HOST_3V3; TP7 = HOST_TX_IN; TP8 = HOST_RX_OUT |
| Test points TP9–TP11 | TP9 = CHIP_RX_OUT; TP10 = CHIP_TX_IN; TP11 = GND |
Each indicator keeps its existing disable jumper. Changing assembly or source selection requires checking the actual schematic and connector orientation. This revision remains an unqualified engineering candidate and has no fabrication release.
Final v19 source SHA-256: 72d83c2ea44912776aab9ae5ad4ea76a93e509f5aac4784576459bf04404bfaa. All six populated/bare top, bottom and isometric views are inspected; their image hashes, 73 model entries and 20 manufacturing/native-check export files match the saved source receipts.