Adapt a specifically qualified low-cost CH340 USB-to-TTL module to a U socket.
Baseline documentation snapshot: 2026-10-11, before the requested connector/protection/usability revision program. New revision features require their own reviewed source and qualification evidence.
This page documents an unqualified engineering study, not a released or tested product. Saved CAD, renders and automated checks do not establish a safe assembly, compatible cable, firmware support or a usable current rating.
Board-specific qualification limits: Native clean retained;130unsigned, host/module/power-order/ESD/fit/physical open.
The table below uses the repository-canonical connector rule: pin 1 is +3.3 V, pin 2 is +5 V, and pin 10 is GND. Do not release a schematic from this table until it is reconciled pin-by-pin with the current V2 Prime connector implementation; current web documentation presents a conflicting ordering.
| Pin | Function | Design note |
|---|---|---|
| 1 | +3.3 V | Canonical fixed rail. |
| 2 | +5 V | Canonical fixed rail. |
| 3 | GPIO! | Board mapping; validate against current V2 hardware before layout. |
| 4 | TX | Board mapping; validate against current V2 hardware before layout. |
| 5 | RX | Board mapping; validate against current V2 hardware before layout. |
| 6 | GPIO/pass-through | Board mapping; validate against current V2 hardware before layout. |
| 7 | UN | Board mapping; validate against current V2 hardware before layout. |
| 8 | UN | Board mapping; validate against current V2 hardware before layout. |
| 9 | UN | Board mapping; validate against current V2 hardware before layout. |
| 10 | GND | Canonical fixed rail. |
Power off before connecting or changing jumpers. Verify pin 1, signal direction, supply voltage and ground at both ends of every cable. A mechanically fitting connector is not proof of electrical compatibility. If a host pin mapping or current allocation remains unresolved in the design record, do not connect the board until it is resolved.
The following are specification requirements or study assumptions; they are not measured operating ratings. A newer selected-revision note takes precedence over historical draft options.
The design describes the following protection intent. Check the selected schematic and remaining qualification gates before relying on it:
Prevent USB-to-host and host-to-USB backfeed; protect exposed UART; define behavior when either side is unpowered.
Complete component review: actualv10 retains translators, actualv07 V2 DCK conversion and existing0402 pull-ups; v06 conversion claim remains rejected. No successor. Native clean retained; host/module/ESD/fit/physical gates unsigned.
Use the configuration and firmware contract for the exact selected revision. Do not copy another module’s socket assignments or assume that an unused pin is available. First-article work must verify source selection, reset/unplug behavior, cable orientation and the actual load or sensor interface before normal operation.
The following are requirements for the next design iterations; this page does not claim they are already fitted:
Documentation route: smoothieware.org/extensions/cheap-uart-adapter-breakout.
The 2026-10-11 upgrade program has saved additional candidates v11, v12, v13. These studies preserve the historical design described above. Their connector, LED, mechanical and protection changes are revision-specific and remain unqualified.
See the per-board changes, failures and remaining work and mandatory family specification. Use the source hash and native check for the exact candidate being reviewed; do not infer hardware ratings from a rendered population.
The three additional revisions are v11, v12, v13. They are engineering studies; saved CAD and renders do not release the hardware. The latest candidate is described below. Older baseline notes above remain historical.
0e38c85d8fa3a3ccee7b94cbda86935a351dfa75dc5b98851258b6c5facd60d2.Applicable protection, current-path, thermal, pinout, cable access and physical tests remain open wherever the linked board record has not verified them. A zero native-error count does not close those gates.
This saved engineering candidate updates revision labels and annotation styling while preserving the electrical geometry, schematic, project rules and baseline files. Independent current checks find zero enabled board errors, open connections, parity errors and schematic-rule errors; 2 board warnings remain. Six current normal-population views and source-bound manufacturing/model hashes were verified for this board.
The documentation URL is still absent from the board. The automatic placement search found no readable clear area while retaining existing annotations; deliberate label reflow remains to be tried. This requirement is pending, and the revision does not establish assembly or fabrication qualification, area savings or priced savings.
a7c14076dd6561851885617961b473c58fe05eadfad7c9ba28835eb4adcdaa71.Earlier revision contracts and readbacks on this page remain historical. Physical connector fit, mounting, fault, current and thermal qualification remain open where applicable.