A small audible indicator for a Smoothieboard v2 (or any 3.3 V / 5 V controller). One control signal turns a buzzer on. It gives a machine an audible “job done”, “alarm”, “probe touched” or “door opened” cue without any firmware work beyond switching one output.
The source document lists only the words “Buzzer module” under OTHER IDEAS. Everything below is the
project’s own definition of that idea; the nine open points in src/questions/buzzer-module/questions.md are
answered in the table at the end of this file.
Baseline documentation snapshot: 2026-10-11, before the requested connector/protection/usability revision program. New revision features require their own reviewed source and qualification evidence.
This page documents an unqualified engineering study, not a released or tested product. Saved CAD, renders and automated checks do not establish a safe assembly, compatible cable, firmware support or a usable current rating.
Board-specific qualification limits: Enabled native checks0;five ignored categories,130unsigned and physical/host/acoustic gates open.
| Input | Connector | Signal | Levels |
|---|---|---|---|
| Gadgeteer control | J1 (Y socket, 2x5, 1.27 mm) pin 3 | active-high GPIO, host side | 3.3 V logic (V2), 0 V low |
| Header control | J3 (3-pin 2.54 mm) pin 3 | active-high, host side | 5 V / 100 mA host output, or 3.3 V; host holds it low with its own 10 k pull-down |
| Power | J1 pin 2 (+5 V) or J3 pin 2 (+5 V) | shared host regulator | 4.5-5.5 V (buzzer operating range 4-7 V) |
Viewed from the front, notch at the bottom (repository interface standard). Pin 1 is +3.3 V, pin 2 +5 V, pin 10 GND on every socket.
| Pin | Y socket function | J1 (host) on this board | J2 (chain) |
|---|---|---|---|
| 1 | +3.3 V | unused, forwarded | direct copper |
| 2 | +5 V | JP1 pad 1 (buzzer power, default); forwarded | direct copper |
| 3 | GPIO | buzzer control, D1 anode 1; forwarded through JP2 | through JP2 |
| 4-9 | GPIO | unused, forwarded | direct copper |
| 10 | GND | ground | direct copper |
3-pin header J3 (viewed from above, pin 1 at the left of the row): 1 = GND, 2 = +5 V, 3 = SIGNAL.
Power off before connecting or changing jumpers. Verify pin 1, signal direction, supply voltage and ground at both ends of every cable. A mechanically fitting connector is not proof of electrical compatibility. If a host pin mapping or current allocation remains unresolved in the design record, do not connect the board until it is resolved.
The following are specification requirements or study assumptions; they are not measured operating ratings. A newer selected-revision note takes precedence over historical draft options.
The design describes the following protection intent. Check the selected schematic and remaining qualification gates before relying on it:
No TVS or fuse is added. Exposure: board-to-board Gadgeteer (no field cable) and a 3-pin header that a user
cables to a host output. The buzzer current (30 mA) is well below the Gadgeteer contact rating and the header
cable rating. A wrong-way 3-pin cable puts the host signal on +5V_HDR: with JP1 open on that side (factory)
the rail is not connected to the buzzer, and the signal pin of the other host would need to be mis-wired to
J3 pin 1 or 2 to cause damage. Reversed-cable and hot-plug behaviour are bench items.
Complete component review: actualv10 retains v03 DMN2056U low-gate upgrade and stock-compatible passive options; no successor. Five ignored native categories and physical/host/acoustic/reservoir gates remain open. Prior design text is historical where superseded by the current contract.
Use the configuration and firmware contract for the exact selected revision. Do not copy another module’s socket assignments or assume that an unused pin is available. First-article work must verify source selection, reset/unplug behavior, cable orientation and the actual load or sensor interface before normal operation.
The following are requirements for the next design iterations; this page does not claim they are already fitted:
Documentation route: smoothieware.org/extensions/buzzer-module.
The 2026-10-11 upgrade program has saved additional candidates v11, v12, v13. These studies preserve the historical design described above. Their connector, LED, mechanical and protection changes are revision-specific and remain unqualified.
See the per-board changes, failures and remaining work and mandatory family specification. Use the source hash and native check for the exact candidate being reviewed; do not infer hardware ratings from a rendered population.
The three additional revisions are v11, v12, v13. They are engineering studies; saved CAD and renders do not release the hardware. The latest candidate is described below. Older baseline notes above remain historical.
bdda8ce4e3d7a0c3c4a0534afbf887345ae29ecf86b8bc7f8ebefbd88dd510d6.JST_PH_B3B-PH-K_1x03_P2.00mm_Vertical. Fit only the selected population; check its pin map and voltage in the design record.Applicable protection, current-path, thermal, pinout, cable access and physical tests remain open wherever the linked board record has not verified them. A zero native-error count does not close those gates.
Protected source v13; current PCB SHA-256 6bc77eda610bb58ec562285216d892c781092cf5743c45742f3bd0db7fafa9a0. Fresh native checks have zero enabled errors/opens/parity/ERC findings and 5 PCB warnings. Exact electrical geometry and project rules unchanged; 40 historical files, 20 model entries,17 exports and 12 current population views verified and inspected. Full documentation URL readable. Both full J3 pin mappings and back title now fit; four title-weight warnings and one dangling supply via remain. No area or priced saving claimed; physical qualification remains open.